/*
 *  Project:            timelyRV_v1.4.x -- a RISCV-32IMC SoC.
 *  Module name:        Testbench.
 *  Description:        Testbench of timelyRV_SoC_hardware.
 *  Last updated date:  2022.10.10.
 *
 *  Copyright (C) 2021-2022 Junnan Li <lijunnan@nudt.edu.cn>.
 *  Copyright and related rights are licensed under the MIT license.
 *
 */

`timescale 1ns/1ps
module fake_clk_wiz_0(
  output  wire  clk_out1,
  output  wire  clk_out2,
  output  wire  locked,
  input   wire  reset,
  input   wire  clk_in1
  );

  assign clk_out1 = clk_in1;
  assign clk_out2 = clk_in1;
  assign locked   = 1'b1;

endmodule
